A feedback equalizer (FBE) has been known in prior art to compensate for the channel dispersion in a communications system. A typical prior art communication system 100 is shown in FIG. 1. The communication system 100 consists of a transmitter 101, a channel 102, and a receiver 103. A typical transmitter 101 includes the following components: an encoder 105 that processes the transmit data (TX data) using a certain encoding scheme, a digital-to-analog converter (DAC) 106 that converts the encoded data into analog voltage waveform, and a low-pass filter (LPF) 107 that filters out the high frequency noises. A typical communications receiver 103 includes the following components: an amplifier (AMP) 108 that compensates for the insertion loss suffered by the transmitted waveform due to the channel 102, a low-pass filter (LPF) 109 that filters out the high-frequency noises, an analog-digital converter (ADC) 110 that converts the analog voltage into digital samples, a feed-forward equalizer (FFE) 111 and a feedback equalizer (FBE) 115 that compensates for the dispersion suffered by the transmitted waveform due to the channel 102, a summer 112, a decision device 113 which determines the most likely encoded TX data transmitted from the transmitter 101, a decoder 114 which performs the decoding and recovers the original TX data. A typical receiver 103 also includes a timing control unit 116 and a voltage controlled oscillator (VCO) 117 or a number controlled oscillator (NCO) 117, which generates a clock signal that is in synchronization with the clock used by the remote transmitter 101. The local clock signal is provided to sample the analog waveform at the input of the ADC 110, and also to synchronize all the digital circuits in the receiver 103.
The above described communication system of FIG. 1 applies to most communication systems that utilize multi-level modulation schemes. For example, PAM-4 (4-level pulse amplitude modulation) is a multi-level modulation scheme that converts the encoded TX data 202 into a 4-level analog waveform 201 as shown in FIG. 2. For a binary signaling scheme, for example, NRZ (non-return-to-zero), there is no need for using sophisticated ADC 110 and DAC 106 devices to handle the multi-level signaling, and the communication system 100 can be simplified, as shown in FIG. 3 as a modified communications system 300. Here, a line driver 304 generates either a high or low voltage depending on whether the encoded TX data (digital data to be transmitted) is 1 or 0. In the receiver 303, the decision unit, timing control unit, and VCO/NCO (voltage controlled oscillator or number controlled oscillator) of FIG. 1 are consolidated in a unit known as clock data recovery (CDR) 309, which reproduces the clock signal used by the remote transmitter 301 and recovers the encoded TX data sent by the remote transmitter 301 over channel 302. Remote transmitter 301 includes encoding 305. Receiver 303 also includes amp 306, FFE 307, summer 308, FBE 311, and decoding 310. The recovered data is labeled as RX data in FIG. 3.
A prior art feedback equalizer (FBE) 400 is shown in FIG. 4. Here, we show a 3-tap FBE 401. The M-level quantizer 402 is a decision device that determines the most likely level. The quantizer output is latched and synchronized by the local recovered clock signal. The quantizer output Dn, also known as the decision, is provided as input to the FBE 401. Inside the FBE, there are two Data Flip Flop (DFF) latches 405 and 406, which store the previous two decisions, Dn-1, and Dn-2. The three decisions (current decision Dn from the quantizer 402, plus the previous two decision Dn-1, and Dn-2) are scaled by three respective gain factors C1, C2, and C3, and the results are summed at summation point 407 to generate the FBE output Yn. The FBE output Yn is subtracted from the input Xn at summation point 404 resulting in the modified input to the M-level quantizer 402 and thus forming a feedback loop.
One problem with the prior art FBE techniques is the critical path in the feedback loop. The critical path is the longest time delay path through a circuit that, in effect, sets the limit on the maximum operating speed of a circuit. In the example of FIG. 4, the current decision from quantizer output Dn needs to be scaled by the gain factor C1, added at summation point 407 to the scaled outputs from the previous decisions two decision Dn-1, and Dn-2, and then subtracted from the quantizer input at summation point 404, and the result needs to be settled before the rising edge of next clock cycle. The output Dn is coupled to decoder 403. For example, in 1 GHz operation of the feedback equalizer of FIG. 4, the contribution Yn needs to settle within 1 nanosecond (1 clock cycle at 1 GHz). This high speed equalization circuit implementation may be very difficult to achieve.
An implementation of a prior art FBE for NRZ receiver is shown in FIG. 5. Note that NRZ is a binary signaling system employing two levels of amplitude, for example +1 and −1. The 2-level quantizer 502 of FIG. 5 can be implemented as a comparator 508 comparing the input, which is Xn−Yn, versus the reference level 0. If the input is greater than the reference level 0, the comparator outputs +1. If the input is less than the reference level 0, the comparator outputs −1. In other words, the comparator outputs +1 if Xn is greater than Yn, otherwise it outputs −1. The comparator output is synchronized by the local recovered clock using a DFF 509, resulting in the current decision Dn, which is fed as input to the FBE 501, which includes DFF 505 and DFF 506. The output D n is coupled to decoder 503. The critical path problem in this example is the same as described above for FIG. 4. What is needed is a FBE that alleviates the critical path problem.